The present disclosure relates to Au-free, low temperature ohmic contacts for III-N power devices on semiconductor substrates and a method of manufacturing thereof.
A GaN-based high electron mobility transistor (HEMT) technology offers perspectives for power device performance beyond known Si limitations. However, such devices are today fabricated on small diameter wafers, and often on sapphire or SiC substrates. To reduce fabrication costs, GaN HEMT power devices could be fabricated on standard Si substrates in high-productivity CMOS production facilities.
GaN HEMT device integration in a Si CMOS platform involves, among other challenges, the implementation of Au-free metallization schemes for source/drain ohmic contacts. A typical metallization scheme includes the deposition of a metal stack directly on top of an AlGaN layer, followed by an anneal step at a sufficiently high temperature to form a metal/AlGaN alloy. In addition, prior to the metal stack deposition, one or several treatments (wet clean, exposure to a plasma, recess etching, n-dopant implantation or diffusion, MOCVD regrowth of a highly n-doped layer in the ohmic areas, and the like) can be applied to the AlGaN/GaN HEMT epi layer. Typically, successful metallization schemes have been using Au-containing metal stacks annealed at relatively high temperatures (≧800° C.); achieving typical contact resistance (Rc) values below 1 Ωmm.
In recent years, several Au-free contact schemes have been proposed, aiming at similarly low Rc. Frequently cited metallization schemes are Ti/Al-based ones, such as Ti/Al/W published by H. S. Lee et. al. in IEEE Electron Device Letters Vol. 32, nr. 5, pp. 623-625 (2011) and Ti/Al/Ni published by M. Alomari et al. in ECS Transactions, Vol. 25, nr. 12, pp. 33-36 (2009). In these cases, Rc below 1.0 Ωmm has only been demonstrated at relatively high annealing temperatures (≧800° C.).
Low Rc and low annealing temperature for Au-free schemes have also been published, but typically employ metal schemes not directly compatible with CMOS platforms, for example, using a Ta/Al metal stack, Rc of 0.06 Ωmm has been reported by A. Malmros et al. in Semicond. Sci. Technol. Vol. 26, p. 075006 (2011). The latter is not directly compatible with CMOS platforms, because Ta is only available in aggressively scaled submicron CMOS technologies typically on a shared Ta/Cu metallization platform to reduce the resistance of the CMOS interconnect layers and hence the RC delay. Using Ta in the ohmic metallization would for this reason result in Cu-contaminated wafers and extra process steps would be needed to remove the Cu-contaminants from the wafer backside, thereby enhancing the cost of the product. Alternatively, low Rc values were obtained with introduction of Si doping in the GaN and/or AlGaN layer. This, however, can cause problems for the breakdown voltage of power devices, and Si implantations in GaN-based layers typically require annealing at very high temperatures (>1000° C.), not compatible with the process flow.